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ordering number : enn * 6728 91799rm (ot) no. 6278-1/39 overview the lc651154n/f/l and the lc651152n/f/l are the small-scale control application versions of sanyo? lc6500 series of 4-bit single-chip cmos microcontrollers, and feature the same basic architecture and instruction set. these microcontrollers include an 8- input 8-bit a/d converter and are appropriate for use in a wide range of applications, from applications with a small number of circuits and controls that were previously implemented in standard logic to applications with a larger scale such as home appliances, automotive equipment, communications equipment, office equipment, and audio equipment such as decks and players. also note that since these ics provide the same basic functions (certain functions and specifications do differ) as, and are pin compatible with the earlier lc651104n/f/l and lc651102n/f/l, they can replace those ics in most cases. features fabricated in a cmos process for low power (a standby function that can be invoked under program control is also provided.) rom/ram lc651154n/f/l ?rom: 4k 8 bits, ram: 256 4 bits lc651152n/f/l ?rom: 2k 8 bits, ram: 256 4 bits instruction set: the 80-instruction set common to the lc6500 family wide operating supply voltage range: 2.2 to 6.0 v (l versions) instruction cycle time: 0.92 ? (f versions) on-chip serial i/o function flexible i/o ports number of ports: 6 ports with a total of 22 pins all ports: ?are i/o ports i/o voltage handling capacity: 15 v (maximum) (open-drain specification c, d, e, and f ports only) output current: 20 ma (maximum) sink current (are capable of directly driving an led.) support options to match application system specifications a. open-drain output, internal pull-up resistor specification: all ports, in bit units b. output level at reset specification: ports c and d can be specified to go to the high or low level in 4-bit units. interrupt function timer interrupts through an interrupt vector (can be tested under program control) int pin and serial i/o full/empty interrupts through an interrupt vector (can be tested under program control) stack levels: 8 (shared with the interrupt system.) timers: 4-bit variable prescaler and 8-bit programmable timers ?clock oscillator options that match a wide range of system specifications oscillator circuit options: two-pin rc oscillator (n and l versions) two-pin ceramic oscillator (n, f, and l versions) clock divider circuit options: no divider, built-in divide-by-3, built-in divide-by-4 (n and l versions) ?continuous square wave output (with a period 64 times the cycle time) a/d converter (successive approximation) 8-bit precision with 8 input channels watchdog timer preliminary lc651154n, 651154f, 651154l, lc651152n, 651152f, 651152l sanyo electric co.,ltd. semiconductor company tokyo office tokyo bldg., 1-10, 1 chome, ueno, taito-ku, tokyo, 110-8534 japan four-bit cmos microcontrollers for small-scale control applications cmos ic any and all sanyo products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft? control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. consult with your sanyo representative nearest you before using any sanyo products described or contained herein in such applications. sanyo assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all sanyo products described or contained herein.
rc circuit time constant optional watchdog timer reset function from an external pin no. 6278-2/39 lc651154n, 651154f, 651154l, 651152n, 651152f, 651152l function table parameter lc651154n/1152n lc651154f/1152f lc651154l/1152l rom 4096 8 bits (1154n) 4096 8 bits (1154f) 4096 8 bits (1154l) memory 2048 8 bits (1152n) 2048 8 bits (1152f) 2048 8 bits (1152l) ram 256 4 bits (1154/1152n) 256 4 bits (1154/1152f) 256 4 bits (1154/1152l) instructions instruction set 80 80 80 table reference supported supported supported interrupts 1 external, 1 internal 1 external, 1 internal 1 external, 1 internal timers 4-bit variable prescaler 4-bit variable prescaler 4-bit variable prescaler on-chip functions + 8-bit timers + 8-bit timers + 8-bit timers stack levels 8 8 8 standby function standby mode entered by the standby mode entered by the standby mode entered by the halt instruction supported halt instruction supported halt instruction supported number of ports 22 i/o port pins 22 i/o port pins 22 i/o port pins serial port input and output in 4 or 8 bit units input and output in 4 or 8 bit units input and output in 4 or 8 bit units i/o voltage handling capability 15 v max. 15 v max. 15 v max. i/o ports output current 10 ma typ. 20 ma max. 10 ma typ. 20 ma max. 10 ma typ. 20 ma max. i/o circuit types open drain (n-channel) and pull-up resistor output options can be specified in 1-bit units output level at reset a high or low level output can be selected in port units (ports c and d only) square wave output supported supported supported minimum cycle time 2.77 ? (v dd 3 3 v) 0.92 ? (v dd 3 2.5 v) 3.84 ? (v dd 3 2.2 v) characteristics supply voltage 3 to 6 v 2.5 to 6 v 2.2 to 6 v current drain 1.5 ma typ. 2 ma typ. 1.5 ma typ. oscillator element rc (800/400 khz typ.) ceramic 4 mhz rc (400 khz typ.) oscillator ceramic (400 k, 800 k, 1 mhz, 4 mhz) ceramic (400 k, 800 k, 1 mhz, 4 mhz) divider circuit option 1/1, 1/3, 1/4 1/1 1/1, 1/3, 1/4 other items package dip30s-d, mfp30s, ssop30 dip30s-d, mfp30s, ssop30 dip30s-d, mfp30s, ssop30 note: recommendations for oscillator elements and oscillator circuit constants will be announced as the recommended circuits for these ics are determined. verify the progress of these developments periodically.
differences between the lc651154n/1152n and the lc651104n/1102n. the table below lists the points that require care when converting an existing product that uses the lc651104n/1102n to use the lc651154n/1152n. no. 6278-3/39 lc651154n, 651154f, 651154l, 651152n, 651152f, 651152l parameter lc651154n/1152n lc651104n/1102n pdmax (1) : dip 310 mw 250 mw allowable power dissipation pdmax (2) : mfp 220 mw 150 mw pdmax (3) : ssop 160 mw (no corresponding package) f cfosc oscillator frequency precision: within ?% [osc1, osc2] changes in the recommended oscillator oscillator frequency precision: within ?% constants (see table 1.) 800 khz typ. (v dd = 3 to 6 v) 900 khz typ. (v dd = 4 to 6 v) constants changed: rext = 5.6 k ? % constants changed: rext = 4.7 k ? % frequency variability (sample to sample): frequency variability (sample to sample): 587 to 1298 khz 634 to 1278 khz 400 khz typ. (v dd = 3 to 6 v) 400 khz typ. (v dd = 3 to 6 v) frequency variability (sample to sample): frequency variability (sample to sample): 290 to 616 khz 276 to 742 khz pull-up resistors ru [res] 200 to 800 k (500 k typ.) 300 to 700 k (500 k typ.) serial clock input clock cycle time t ckcy (1) [ sck] min. 2.0 ? min. 3.0 ? a/d converter characteristics operating voltage v dd = 3 to 6 v v dd = 4 to 6 v av+ = v dd reference input current 200 to 800 ? (500 ? typ.) 75 to 300 ? (150 ? typ.) av?= v ss irif [av+, av? watchdog timer cw = 0.047 ?% ? v dd = 3 to 6 v v dd = 4 to 6 v rw = 680 ?% k ri = 100 ?% package dip30s-d, mfp30s dip30s-d, mfp30s an ssop30 version was added. differences between the lc651154f/1152f and the lc651104f/1102f. the table below lists the points that require care when converting an existing product that uses the lc651104f/1102f to use the lc651154f/1152f. parameter lc651154f/1152f lc651104f/1102f pdmax (1) : dip 310 mw 250 mw allowable power dissipation pdmax (2) : mfp 220 mw 150 mw pdmax (3) : ssop 160 mw (no corresponding package) operating supply voltage v dd 2.5 to 6 v 4 to 6 v specifications for v dd = 4 to 6 v low-level input voltage v il (n) the specifications for v dd = 2.5 to 6 v specifications for v dd = 4 to 6 v were added. oscillator characteristics ceramic oscillator oscillator frequency precision: within ? % oscillator frequency precision: within ? % oscillator frequency pull-up resistors ru [res] 200 to 800 k (500 k typ.) 300 to 700 k (500 k typ.) operating voltage ad speed 1/1 : v dd = 3.5 to 6 v ad speed 1/1 : v dd = 4.5 to 6 v ad speed 1/2 : v dd = 3 to 6 v ad speed 1/2 : v dd = 4 to 6 v reference input current 200 to 800 ? (500 ? typ.) 75 to 300 ? (150 ? typ.) irif [av+, av? package dip30s-d, mfp30s dip30s-d, mfp30s an ssop30 version was added. oscillator characteristics ceramic oscillator oscillator frequency 2-pin rc oscillator oscillator frequency f mosc [osc1, osc2] f cfosc [osc1, osc2] a/d converter characteristics av+ = v dd av?= v ss
no. 6278-4/39 lc651154n, 651154f, 651154l, 651152n, 651152f, 651152l differences between the lc651154l/1152l and the lc651104l/1102l. the table below lists the points that require care when converting an existing product that uses the lc651104l/1102l to use the lc651154l/1152l. caution: perform a full system evaluation and inspection after replacing the microcontroller. parameter lc651154l/1152l lc651104l/1102l pdmax (1) : dip 310 mw 250 mw allowable power dissipation pdmax (2) : mfp 220 mw 150 mw pdmax (3) : ssop 160 mw (no corresponding package) operating supply voltage v dd 2.2 to 6 v 2.5 to 6 v oscillator frequency precision: within ?% changes in the recommended oscillator oscillator frequency precision: within ?% constants (see table 1.) 400 khz typ. (v dd = 2.2 to 6 v) 400 khz typ. (v dd = 2.5 to 6 v) frequency variability (sample to sample): frequency variability (sample to sample): 290 to 841 khz 276 to 742 khz pull-up resistors ru [res] 200 to 800 k (500 k typ.) 300 to 700 k (500 k typ.) serial clock input clock cycle time t ckcy (1) [ sck] min. 2.0 ? min. 6.0 ? a/d converter characteristics operating voltage v dd = 3 to 6 v v dd = 4 to 6 v av+ = v dd reference input current 200 to 800 ? (500 ? typ.) 75 to 300 ? (150 ? typ.) av?= v ss irif [av+, av? watchdog timer v dd = 2.2 to 6.0 v v dd = 2.5 to 6.0 v package dip30s-d, mfp30s dip30s-d, mfp30s an ssop30 version was added. oscillator characteristics ceramic oscillator oscillator frequency 2-pin rc oscillator oscillator frequency f cfosc [osc1, osc2] f mosc [osc1, osc2]
pin assignment the pin assignment is the same for the dip, mfp, and ssop packages. no. 6278-5/39 lc651154n, 651154f, 651154l, 651152n, 651152f, 651152l
system block diagram no. 6278-6/39 lc651154n, 651154f, 651154l, 651152n, 651152f, 651152l pin functions osc1, osc2: connections for the oscillator capacitor and resistor or ceramic element test: ic testing. res: reset int: interrupt request input pa0 to pa3: common i/o ports a0 to a3 si: serial input pc0 to pc3: common i/o ports c0 to c3 so: serial output pd0 to pd3: common i/o ports d0 to d3 sck: serial clock input output pe0 to pe3: common i/o ports e0 to e3 ad0 to ad7: a/d converter analog inputs pf0 to pf3: common i/o ports f0 to f3 av + , av : a/d converter reference voltage inputs pg0 to pg3: common i/o ports g0 to g3 wdr: watchdog timer reset input note: pins si, so, sck, and int are shared function pins also used as pf0:3. ram: data memory rom: program memory f: flag pc: program counter wr: working register int: interrupt control ac: accumulator ir: instruction register alu: arithmetic and logic unit i.dec: instruction decoder dp: data pointer cf, csf: carry flag and carry save flag e: e register zf, zsf: zero flag and zero save flag ctl: control register extf: external interrupt request flag osc: oscillator circuit tmf: internal interrupt request flag tm: timer sts: status register shared with port f
development support the following are provided for development with the lc651154 and lc651152. user? manual see the ?c651104/1102 user? manual. development tools manual see the ?our-bit microcontroller eva86000 development tools manual. software manual ?c65/66 series software manual ?development tools program development (eva86000 system) on-chip eprom microcontroller for program evaluation no. 6278-7/39 lc651154n, 651154f, 651154l, 651152n, 651152f, 651152l pin functions symbol number i/o function option at reset handling when of pins unused v dd v ss 1 power supply osc1 1 input connection for the rc circuit or ceramic oscillator element used for the system clock oscillator leave osc2 open when an external clock input is used. (1) two-pin rc oscillator or external clock (2) two-pin ceramic oscillator (3) divider option 1. no divider 2. divide-by-3 3. divide-by-4 i/o port a0 to a3 input in 4-bit units (ip instruction) output in 4-bit units (op instruction) testing in 1-bit units (bp and bnp instructions) set and reset in 1-bit units (spb and rpb instructions) pa3 is used for standby mode control application must assure that chattering does not occur on the pa3 input during halt instruction execution. all four pins have shared functions pa0/ad0 - a/d converter input ad0 pa1/ad1 - a/d converter input ad1 pa2/ad2 - a/d converter input ad2 pa3/ad3 - a/d converter input ad3 (1) open-drain output (2) pull-up resistor options (1) and (2) can be specified in bit units high-level output (the output n- channel transistors in the off state.) select the open-drain output option and connect to v ss . osc2 1 output pa0 to pa3/ ad0 to ad3 4 i/o i/o port c0 to c3 the port functions are identical to those of pa0 to pa3. (see note.) the output during a reset can be selected to be either high or low as an option. note: this port has no standby mode control function. (1) open-drain output (2) pull-up resistor (3) high-level output during reset (4) low-level output during reset options (1) and (2) can be specified in bit units options (3) and (4) are specified 4 bits at a time high-level output low-level output (depending on option selected.) the same as for pa0 to pa3 pc0 to pc3 4 i/o i/o port d0 to d3 the port functions and options are identical to those of pc0 to pc3. the same as pc0 to pc3 the same as pc0 to pc3 the same as for pa0 to pa3 pd0 to pd3 4 i/o continued on next page.
no. 6278-8/39 lc651154n, 651154f, 651154l, 651152n, 651152f, 651152l continued from preceding page. symbol number i/o function option at reset handling when of pins unused pe0-pe1/ wdr 2 i/o i/o port e0 to e1 input in 4-bit units (ip instruction) output in 4-bit units (op instruction) set and reset in 1-bit units (spb and rpb instructions) testing in 1-bit units (bp and bnp instructions) pe0 also has a continuous pulse (64?cyc) output function. pe1 becomes the watchdog reset pin wdr when selected for such as an option. (1) open-drain output (2) pull-up resistor options (1) and (2) can be specified in bit units (3) normal port pe1 (4) watchdog reset wdr ?either options (3) and (4) may be specified. high-level output (the output n- channel transistors in the off state.) identical to those for pa0 to pa3 pf0/si pf1/so pf2/sck pf3/int 4 i/o i/o port f0 to f3 the port functions and options are identical to those of pe0 to pe1 (see note.) pf0 to pf3 have shared functions as the serial interface pins and the int input. the function can be selected under program control. si ... serial input pin so ... serial output pin sck ... input and output of the serial clock signal int ... interrupt request input the serial i/o function can be switched between 4- bit and 8-bit transfers under program control. note: there is no continuous pulse output function. identical to those for pa0 to pa3 identical to those for pa0 to pa3 the serial port functions are disabled. the interrupt source is set to int. identical to those for pa0 to pa3 pg0-pg3/ ad4-ad7 4 i/o i/o port g0 to g3 the port functions and options are identical to those of pe0 to pe1 (see note.) note: there is no continuous pulse output function. all four pins have shared functions. pg0/ad4 - a/d converter input ad4 pg1/ad5 - a/d converter input ad5 pg2/ad6 - a/d converter input ad6 pg3/ad7 - a/d converter input ad7 identical to those for pa0 to pa3 identical to those for pa0 to pa3 identical to those for pa0 to pa3 av + 1 a/d converter reference voltage input connect to v ss . system reset input applications must provide an external capacitor for the power-on reset. apply a low level to this pin for 4 clock cycles to effect and reset start. av 1 res 1 input ic test pin this pin must be connected to v ss during normal operation. this pin must be connected to v ss . test 1 input
no. 6278-9/39 lc651154n, 651154f, 651154l, 651152n, 651152f, 651152l oscillator circuit options option circuit conditions and other notes ceramic oscillator element divider circuit options option circuit conditions and other notes this option can be used with any of the three oscillator options. the oscillator frequency or external clock frequency must not exceed 1444 khz. (lc651154n, lc651152n) the oscillator frequency or external clock frequency must not exceed 4330 khz. (lc651154f, lc651152f) the oscillator frequency or external clock frequency must not exceed 1040 khz. (lc651154l, LC651152L) ?this option can only be used with the external clock and the ceramic oscillator options. ?the oscillator frequency or external clock frequency must not exceed 4330 khz. ?this option can only be used with the external clock and the ceramic oscillator options. ?the oscillator frequency or external clock frequency must not exceed 4330 khz. oscillator circuit caution: the following tables summarize the oscillator and divider circuit options. use care when selecting these options. timing generator oscillator circuit oscillator circuit timing generator timing generator external clock two-pin rc oscillator ceramic oscillator the osc2 pin must be left open. no divider built-in divide-by-three circuit built-in divide-by-four circuit divide-by-3 divide-by-4
no. 6278-10/39 lc651154n, 651154f, 651154l, 651152n, 651152f, 651152l lc651154n, lc651152n oscillator options circuit type frequency divider option v dd range notes (cycle time) 400 khz 1/1 (10 ?) 3 to 6 v cannot be used with the divide-by-three and divide-by-four options. 1/1 (5 ?) 3 to 6 v 800 khz 1/3 (15 ?) 3 to 6 v 1/4 (20 ?) 3 to 6 v 1/1 (4 ?) 3 to 6 v 1 mhz 1/3 (12 ?) 3 to 6 v 1/4 (16 ?) 3 to 6 v 4 mhz 1/3 (3 ?) 3 to 6 v cannot be used with the no divider circuit 1/4 (4 ?) 3 to 6 v option. 200 k to 1444 khz 1/1 (20 to 2.77 ?) 3 to 6 v 600 k to 4330 khz 1/3 (20 to 2.77 ?) 3 to 6 v 800 k to 4330 khz 1/4 (20 to 3.70 ?) 3 to 6 v use the no divider circuit option and the 3 to 6 v recommended circuit constants. if using other circuit constants is unavoidable, the application must use a frequency identical to the external clock and observe the v dd range specification. external clock used with the ceramic oscillator option external clock drive is not possible. to use external clock drive, select the 2-pin rc oscillator option. lc651154f, lc651152f circuit type frequency divider option v dd range notes (cycle time) ceramic oscillator 4 mhz 1/1 (1 ?) 2.5 to 6 v external clock used with the 2-pin rc oscillator circuit 200 k to 4330 khz 1/1 (20 to 0.92 ?) 2.5 to 6 v external clock used with the ceramic oscillator option external clock drive is not possible. to use external clock drive, select the 2-pin rc oscillator option. ceramic oscillator external clock used with the 2-pin rc oscillator circuit two-pin rc
no. 6278-11/39 lc651154n, 651154f, 651154l, 651152n, 651152f, 651152l lc651154l, LC651152L circuit type frequency divider option v dd range notes (cycle time) 400 khz 1/1 (10 ?) 2.2 to 6 v cannot be used with the divide-by-three and divide-by-four options. 1/1 (5 ?) 2.2 to 6 v 800 khz 1/3 (15 ?) 2.2 to 6 v 1/4 (20 ?) 2.2 to 6 v 1/1 (4 ?) 2.2 to 6 v 1 mhz 1/3 (12 ?) 2.2 to 6 v 1/4 (16 ?) 2.2 to 6 v cannot be used with either the no divider 4 mhz 1/4 (4 ?) 2.2 to 6 v circuit option or the divide-by-three circuit option. 200 k to 1040 khz 1/1 (20 to 3.84 ?) 2.2 to 6 v 600 k to 3120 khz 1/3 (20 to 3.84 ?) 2.2 to 6 v 800 k to 4160 khz 1/4 (20 to 3.84 ?) 2.2 to 6 v use the no divider circuit option and the 2.2 to 6 v recommended circuit constants. if using other circuit constants is unavoidable, the application must use a frequency identical to the external clock and observe the v dd range specification. external clock used with the ceramic oscillator option external clock drive is not possible. to use external clock drive, select the 2-pin rc oscillator option. port c and d output level during reset option the output level during a reset can be selected from the two options below in 4-bit units for the c and d ports. port output type option the following two options may be selected for the i/o ports individually (bit units). watchdog reset option this option allows the pe1/wdr pin to be selected either to be used as the normal port pe1 or to be used as the watchdog reset pin wdr. option conditions and other notes high-level output during reset ports c and d in 4-bit units low-level output during reset ports c and d in 4-bit units option circuit applicable ports ceramic oscillator external clock used with the 2-pin rc oscillator circuit two-pin rc 1. open-drain output 2. built-in pull-up resistor ports a, c, d, e, f, and g
lc651154n, 651152n no. 6278-12/39 lc651154n, 651154f, 651154l, 651152n, 651152f, 651152l parameter symbol conditions applicable pins and notes ratings unit maximum supply voltage v dd max v dd ?.3 to +7.0 output voltage v o osc2 allowed up to the generated voltage. input voltage v i (1) osc1 * 1 ?.3 to v dd + 0.3 v v i (2) test, res, av + , av ?.3 to v dd + 0.3 v io (1) pc0 to 3, pd0 to 3, pe0, 1, pf0 to 3 open-drain specification ports ?.3 to +15 i/o voltage v io (2) pc0 to 3, pd0 to 3, pe0, 1, pf0 to 3 pull-up resistor specification ports ?.3 to v dd + 0.3 v io (3) pc0 to 3, pg0 to 3 ?.3 to v dd + 0.3 peak output current i op i/o ports ? to +20 i oa per single pin, averaged over 100 ms i/o ports ? to +20 the total current for pc0 to pc3, pc0 to 3 i oa (1) pd0 to pd3, and pe0 to pe1 * 2 pd0 to 3 ?5 to +100 ma average output current pe0 to 1 the total current for pf0 to pf3, pf0 to 3 i oa (2) pg0 to pg3, and pa0 to pa3 (see note 2.) * 2 pg0 to 3 ?5 to +100 pa0 to 3 pd max (1) ta = ?0 to +85? (dip package) 310 allowable power dissipation pd max (2) ta = ?0 to +85? (mfp package) 220 mw pd max (3) ta = ?0 to +85? (ssop package) 160 operating temperature topr ?0 to +85 ? storage temperature tstg ?5 to +125 absolute maximum ratings at ta = 25?, v ss = 0 v parameter symbol conditions applicable pins and notes ratings unit min typ max operating supply voltage v dd v dd 3.0 6.0 standby supply voltage v st ram and register values retained * 3 v dd 1.8 6.0 v ih (1) output n-channel transistors off ports c, d, e, and f with 0.7 v dd 13.5 open-drain specifications v ih (2) output n-channel transistors off ports c, d, e, and f with 0.7 v dd v dd pull-up resistor specifications v ih (3) output n-channel transistors off port a, g 0.7 v dd v dd v the int, sck, and si high-level input voltage v ih (4) output n-channel transistors off pins with open-drain 0.8 v dd 13.5 specifications the int, sck, and si v ih (5) output n-channel transistors off pins with pull-up resistor 0.8 v dd v dd specifications v ih (6) v dd = 1.8 to 6.0 v res 0.8 v dd v dd v ih (7) external clock specifications osc1 0.8 v dd v dd allowable operating ranges at ta = ?0 to +85?, v ss = 0 v, v dd = 3.0 to 6.0 v (unless otherwise specified.) continued on next page.
no. 6278-13/39 lc651154n, 651154f, 651154l, 651152n, 651152f, 651152l parameter symbol conditions applicable pins ratings unit and notes min typ max v il (1) output n-channel transistors off v dd = 4 to 6 v port v ss 0.3 v dd v il (2) output n-channel transistors off v dd = 3 to 6 v port v ss 0.25 v dd v il (3) output n-channel transistors off v dd = 4 to 6 v int, sck, si v ss 0.25 v dd v il (4) output n-channel transistors off v dd = 3 to 6 v int, sck, si v ss 0.2 v dd low-level input voltage v il (5) external clock specifications v dd = 4 to 6 v osc1 v ss 0.25 v dd v v il (6) external clock specifications v dd = 3 to 6 v osc1 v ss 0.2 v dd v il (7) v dd = 4 to 6 v test v ss 0.3 v dd v il (8) v dd = 3 to 6 v test v ss 0.25 v dd v il (9) v dd = 4 to 6 v res v ss 0.25 v dd v il (10) v dd = 3 to 6 v res v ss 0.2 v dd the clock may have a frequency up to 4.33 mhz operating frequency fop (tcyc) when either the divide-by- v dd = 3 to 6 v 200 1444 khz (?) (cycle time) three or divide-by-four (20) (2.77) internal divider circuit option is used. external clock conditions figure 1. frequency text v dd = 3 to 6 v osc1 200 4330 khz pulse width texth, textl v dd = 3 to 6 v osc1 69 ns rise and fall times textr, textf v dd = 3 to 6 v osc1 50 recommended oscillator circuit constants cext figure 2 v dd = 3 to 6 v osc1, osc2 270 ?% pf rext 12 ?% k two-pin rc oscillator cext figure 2 v dd = 3 to 6 v osc1, osc2 270 ?% pf rext 5.6 ?% k ceramic oscillator * 4 figure 3 see table 1. continued from preceding page. either the divide-by- three or divide-by-four internal divider circuit must be used if the clock frequency exceeds 1.444 mhz.
no. 6278-14/39 lc651154n, 651154f, 651154l, 651152n, 651152f, 651152l parameter symbol conditions applicable pins and notes ratings unit min typ max ?output n-channel transistors off i ih (1) (including the n-channel transistor 5.0 off leakage current.) ?v in = 13.5 v high-level input current ?output n-channel transistors off i ih (2) (including the n-channel transistor ports a and g with the 1.0 ? off leakage current.) open-drain specifications ?v in = v dd i ih (3) when an external clock is used, osc1 1.0 v in = v dd i il (1) ?output n-channel transistors off ports with the open-drain ?.0 ?v in = v ss specifications i il (2) ?output n-channel transistors off ports with the pull-up ?.3 ?.35 ma low-level input current ?v in = v ss resistor specifications i il (3) v in = v ss res ?5 ?0 i il (4) when an external clock is used, osc1 ?.0 ? v in = v ss v oh (1) ?i oh = ?0 ? ports with the pull-up v dd ?1.2 high-level output voltage ?v dd = 4.0 to 6.0 v resistor specifications v oh (2) i oh = ?0 ? ports with the pull-up v dd ?0.5 resistor specifications v ol (1) ?i ol = 10 ma port 1.5 low-level output voltage ?v dd = 4.0 to 6.0 v v ol (2) when i ol = 1 ma and the i ol for port 0.5 v each port is 1 ma or less. hysteresis voltage v his 0.1 v dd high-level threshold v th 0.4 v dd 0.8 v dd voltage low-level threshold v tl 0.2 v dd 0.6 v dd voltage current drain * 6 ?operating, with the output iddop (1) n-channel transistors off v dd 1.5 4 two-pin rc oscillator ?with the ports at v dd ?figure 2, fosc = 800 khz (typical) ceramic oscillator iddop (2) figure 3, 4 mhz, divide-by-three circuit used v dd 1.5 5 iddop (3) figure 3, 4 mhz, divide-by-four circuit used v dd 1.5 4 iddop (4) ?figure 3, 400 khz v dd 1.0 2.5 ma iddop (5) ?figure 3, 800 khz v dd 1.5 4 ?200 khz to 1444 khz, no divider circuit external clock iddop (6) ?600 khz to 4330 khz, divide-by- v dd 1.5 5 three circuit used ?800 khz to 4330 khz, divide-by- four circuit used output n-channel transistors off, v dd 0.05 10 standby mode iddst v dd = 6 v ? ports at v dd , v dd = 3 v v dd 0.025 5 electrical characteristics at ta = ?0 to +85?, v ss = 0 v, v dd = 3.0 to 6.0 v (unless otherwise specified.) schmitt characteristics continued on next page. res, int, sck, si, and osc1 with schmitt specifications * 5 ports c, d, e and f with the open-drain specifications
no. 6278-15/39 lc651154n, 651154f, 651154l, 651152n, 651152f, 651152l parameter symbol conditions applicable pins and notes ratings unit min typ max oscillator characteristics ?figure 3, fo = 400 khz osc1, osc2 392 400 408 ?figure 3, fo = 800 khz osc1, osc2 784 800 816 ceramic oscillator f cfosc * 7 ?figure 3, fo = 1 mhz osc1, osc2 980 1000 1020 khz oscillator frequency ?figure 3, fo = 4 mhz, with the osc1, osc2 3920 4000 4080 divide-by-three or divide-by-four circuit used. oscillator stabilization time ?figure 4, fo = 400 khz 10 (note 8) t cfs ?figure 4, fo = 800 khz, 1 mhz, or 10 ms 4 mhz, with the divide-by-three or divide-by-four circuit used. two-pin rc oscillator ?figure 2, cext = 270 pf ?% osc1, osc2 587 800 1298 oscillator frequency f mosc ?figure 2, rext = 5.6 k ?% khz ?figure 2, cext = 270 pf ?% osc1, osc2 290 400 818 ?figure 2, rext = 12 k ?% pull-up resistor rpp ?output n-channel transistors off pull-up resistor 814 30 i/o ports ?v in = v ss , v dd = 5 v specification ports k res ru v in = v ss , v dd = 5 v res 200 500 800 external reset characteristics t rst see figure 5. reset time ?f = 1 mhz pin capacitances cp ?with all pins other than the pin 10 pf being tested at v in = v ss . serial clock input clock cycle time t ckcy (1) figure 6 sck 2.0 output clock cycle time t ckcy (2) figure 6 sck 64 tcyc * 9 input clock low-level pulse t ckl (1) figure 6 sck 1.0 width output clock low-level pulse t ckl (2) figure 6 sck 32 tcyc width input clock high-level pulse t ckh (1) figure 6 sck 1.0 width output clock high-level t ckh (2) figure 6 sck 32 tcyc pulse width serial input data setup time t ick si 0.4 data hold time t cki si 0.4 serial output ?stipulated with respect to the falling edge of sck. ?with an external resistor of 1 k output delay time t cko and an external capacitor of 50 pf so 0.6 on only the n-channel open-drain pins. ?figure 6 continued from preceding page. continued on next page. ?stipulated with respect to the rising edge of sck. ?figure 6 ?
no. 6278-16/39 lc651154n, 651154f, 651154l, 651152n, 651152f, 651152l continued from preceding page. parameter symbol conditions applicable pins ratings unit and notes min typ max pulse output function t pcy pe0 64 t cyc period high-level pulse width t ph pe0 32 t cyc ?0% ? low-level pulse width t pl pe0 32 t cyc ?0% resolution 8 bit absolute precision av + = v dd ? ? lsb av = v ss when the a/d converter 72 312 speed is normal (1:1), (t cyc = (t cyc = namely 26 t cyc 2.77 ?) 12 ?) conversion time tcad when the a/d converter 141 612 ? speed is one half (1:2), (t cyc = (t cyc = namely 51 t cyc 2.77 ?) 12 ?) input reference voltage av + av + av v dd v av av v ss av + input reference current irif av + = v dd , av = v ss av + , av 200 500 800 ? range analog input voltage v ain ad0 to ad7 av av + v range including the output off ad0 to ad7 1 leakage current. (the i/o v ain = v dd shared analog port input current i ain function ports ? v ain = v ss have open- ? drain specifications.) cw when pe1 has the wdr 0.1 ?% f open-drain specifications. recommended rw when pe1 has the wdr 680 ?% k constants * 10 open-drain specifications. ri when pe1 has the wdr 100 ?% open-drain specifications. clear time (discharge) t wct figure 8 wdr 100 ? clear period (charge) t wccy figure 8 wdr 36 ms cw when pe1 has the wdr 0.047 ?% f open-drain specifications. recommended rw when pe1 has the wdr 680 ?% k constants * 10 open-drain specifications. ri when pe1 has the wdr 100 ?% open-drain specifications. clear time (discharge) t wct figure 8 wdr 40 ? clear period (charge) t wccy figure 8 wdr 18 ms a/d converter characteristics watchdog timer notes:1. allowed up to the amplitude generated when the oscillator shown in figure 3 is used with the recommended circuit consta nts and driven by the ic. 2. the average over a 100 ms period. 3. the operating v dd supply voltage must be maintained from the point the halt instruction is executed until the ic has fully entered the standby state. applications must also assure that no chattering occurs on the pa3 pin during the halt instruction execution cycle. 4. recommended circuit constants that have been verified to oscillate stably according to the oscillator element manufacturer us ing the sanyo- stipulated oscillator characteristics evaluation board. 5. the osc1 pin will have schmitt characteristics when external clock oscillator is selected with the two-pin rc oscillator opti on. 6. these are the results of testing using our (sanyo?) characteristics evaluation board with the recommended circuit constants used as external components. the current flowing in the ic? output transistors and transistors that have pull-up resistors is not included. 7. f cfosc is the frequency when the recommended circuit constants from table 1 are used as external components. 8. indicates the time required to achieve stable oscillation from the point v dd rises above the lower limit of the operating voltage range. 9. tcyc = 4 the system clock period 10. if the application could be used in an environment in which condensation is possible, extra care with respect to the leakage between pe1 and adjacent pins and leakage associated with external resistors and capacitor is required during design. v dd = 3 to 6 v v dd = 3 to 6 v v dd = 3 to 6 v ?figure 7 ?t cyc = 4 system clock period ?with an external resistor of 1 k and an external capacitor of 50 pf on only the n-channel open-drain pins.
no. 6278-17/39 lc651154n, 651154f, 651154l, 651152n, 651152f, 651152l external clock figure 1 external clock input waveform figure 2 two-pin rc oscillator circuit figure 3 ceramic oscillator circuit open ceramic oscillator element
no. 6278-18/39 lc651154n, 651154f, 651154l, 651152n, 651152f, 651152l stable oscillation figure 4 oscillation stabilization time figure 5 reset circuit note: if the power supply rise time is zero, the reset time when cres = 0.1 ? will be between 10 and 100 ms. if the power supply rise time is long, increase the value of cres so that the reset time is at least 10 ms. table 1 recommended ceramic oscillator circuit constants 4 mhz (murata mfg. co., ltd.) c1 33 pf ?0% csa4.00mg c2 33 pf ?0% cst4.00mgw (internal capacitor) r 0 4 mhz (kyocera corporation) c1 33 pf ?0% kbr4.0msa c2 33 pf ?0% kbr4.0mks (internal capacitor) r 0 1 mhz (murata mfg. co., ltd.) c1 100 pf ?0% csb1000j c2 100 pf ?0% r 3.3 k 800 khz (murata mfg. co., ltd.) c1 100 pf ?0% csb800j c2 100 pf ?0% r 3.3 k 400 khz (murata mfg. co., ltd.) c1 220 pf ?0% csb400p c2 220 pf ?0% r 3.3 k oscillation stabilization time t cfs lower limit for the operating supply voltage
no. 6278-19/39 lc651154n, 651154f, 651154l, 651152n, 651152f, 651152l input data figure 6 serial i/o timing the load conditions are the same as those in figure 5. figure 7 port pe0 pulse output timing t wccy : the charge time due to the time constant of the circuit consisting of the external components cw, rw, and rl. t wct : the discharge time due to software processing. figure 8 watchdog timer waveform output data load circuit
rc oscillator characteristics for the lc651154n and lc651152n figure 9 shows the rc oscillator characteristics for the lc651154n and lc651152n. however, the sample-to-sample variation in the lc651154n and lc651152n rc oscillator frequency described below does occur. 1) when: v dd = 3.0 to 6.0 v, ta = ?0 to +85? external constants: cext = 270 pf rext = 12.0 k f mosc will be: 290 khz f mosc 818 khz 2) when: v dd = 3.0 to 6.0 v, ta = ?0 to +85? external constants: cext = 270 pf rext = 5.6 k f mosc will be: 587 khz f mosc 1298 khz therefore, only the above circuit constants are recommended. if use of circuit constants other than the above is unavoidable, they must be in the following ranges. cext = 150 to 390 pf rext = 3 to 20 k (see figure 9.) notes the oscillator frequency must be in the range 350 to 850 khz when v dd = 5.0 v and ta = 25?. applications must be designed to have adequate margins so that the oscillator frequency falls in the operating clock frequency range (see the oscillator divider option table) for the voltage range v dd = 3.0 to 6.0 v and for the temperature range ta = ?0 to +85?. no. 6278-20/39 lc651154n, 651154f, 651154l, 651152n, 651152f, 651152l these characteristics curves are for reference purposes only and are not guaranteed. figure 9 rc oscillator frequency data (representative values)
no. 6278-21/39 lc651154n, 651154f, 651154l, 651152n, 651152f, 651152l lc651154f, 651152f absolute maximum ratings at ta = 25?, v ss = 0 v parameter symbol conditions applicable pins and notes ratings unit maximum supply voltage v dd max v dd ?.3 to +7.0 output voltage v o osc2 allowed up to the generated voltage. input voltage v i (1) osc1 * 1 ?.3 to v dd + 0.3 v v i (2) test, res, av + , av ?.3 to v dd + 0.3 v io (1) pc0 to pc3, pd0 to pd3, pe0, 1, pf0 to pf3 open-drain specification ports ?.3 to +15 i/o voltage v io (2) pc0 to pc3, pd0 to pd3, pe0, 1, pf0 to pf3 pull-up resistor specification ports ?.3 to v dd + 0.3 v io (3) pa0 to pa3, pg0 to pg3 ?.3 to v dd + 0.3 peak output current i op i/o ports ? to +20 i oa per single pin, averaged over 100 ms i/o ports ? to +20 the total current for pc0 to pc3, pc0 to pc3 i oa (1) pd0 to pd3, and pe0 and pe1 * 2 pd0 to pd3 ?5 to +100 ma average output current pe0 and pe1 the total current for pf0 to pf3, pg0 to pg3, pf0 to pf3 i oa (2) and pa0 to pa3 (see note 2.) * 2 pg0 to pg3 ?5 to +100 pa0 to pa3 pd max (1) ta = ?0 to +85? (dip package) 310 allowable power dissipation pd max (2) ta = ?0 to +85? (mfp package) 220 mw pd max (3) ta = ?0 to +85? (ssop package) 160 operating temperature topr ?0 to +85 ? storage temperature tstg ?5 to +125 parameter symbol conditions applicable pins and notes ratings unit min typ max operating supply voltage v dd v dd 2.5 6.0 standby supply voltage v st ram and register values retained * 3 v dd 1.8 6.0 v ih (1) output n-channel transistors off ports c, d, e, and f with 0.7 v dd 13.5 open-drain specifications v ih (2) output n-channel transistors off ports c, d, e, and f with 0.7 v dd v dd pull-up resistor specifications v ih (3) output n-channel transistors off port a, g 0.7 v dd v dd v the int, sck, and si high-level input voltage v ih (4) output n-channel transistors off pins with open-drain 0.8 v dd 13.5 specifications the int, sck, and si v ih (5) output n-channel transistors off pins with pull-up resistor 0.8 v dd v dd specifications v ih (6) v dd = 1.8 to 6.0 v res 0.8 v dd v dd v ih (7) external clock specifications osc1 0.8 v dd v dd allowable operating ranges at ta = ?0 to +85?, v ss = 0 v, v dd = 2.5 to 6.0 v (unless otherwise specified.) continued on next page.
no. 6278-22/39 lc651154n, 651154f, 651154l, 651152n, 651152f, 651152l parameter symbol conditions applicable pins ratings unit and notes min typ max v il (1) output n-channel transistors off v dd = 4 to 6 v port v ss 0.3 v dd v il (2) output n-channel transistors off v dd = 2.5 to 6 v port v ss 0.2 v dd v il (3) output n-channel transistors off v dd = 4 to 6 v int, sck, si v ss 0.25 v dd v il (4) output n-channel transistors off v dd = 2.5 to 6 v int, sck, si v ss 0.15 v dd low-level input voltage v il (5) external clock specifications v dd = 4 to 6 v osc1 v ss 0.25 v dd v v il (6) external clock specifications v dd = 2.5 to 6 v osc1 v ss 0.15 v dd v il (7) v dd = 4 to 6 v test v ss 0.3 v dd v il (8) v dd = 2.5 to 6 v test v ss 0.2 v dd v il (9) v dd = 4 to 6 v res v ss 0.25 v dd v il (10) v dd = 2.5 to 6 v res v ss 0.15 v dd operating frequency fop (tcyc) 200 4330 khz (?) (cycle time) (20) (0.92) external clock conditions frequency text osc1 200 4330 khz pulse width texth, textl figure 1. osc1 69 ns rise and fall times textr, textf osc1 50 ns recommended oscillator circuit constants figure 2 see table 1. ceramic oscillator * 4 parameter symbol conditions applicable pins and notes ratings unit min typ max ?output n-channel transistors off ports c, d, e and f with i ih (1) (including the n-channel transistor the open-drain 5.0 off leakage current.) specifications ?v in = 13.5 v high-level input current ?output n-channel transistors off i ih (2) (including the n-channel transistor ports a and g with the 1.0 ? off leakage current.) open-drain specifications ?v in = v dd i ih (3) when an external clock is used, osc1 1.0 v in = v dd i il (1) ?output n-channel transistors off ports with the open-drain ?.0 ?v in = v ss specifications i il (2) ?output n-channel transistors off ports with the pull-up ?.3 ?.35 ma low-level input current ?v in = v ss resistor specifications i il (3) v in = v ss res ?5 ?0 i il (4) when an external clock is used, osc1 ?.0 ? v in = v ss v oh (1) ?i oh = ?0 ? ports with the pull-up v dd ?1.2 high-level output voltage ?v dd = 4.0 to 6.0 v resistor specifications v oh (2) i oh = ?0 ? ports with the pull-up v dd ?0.5 resistor specifications v ol (1) ?i ol = 10 ma port 1.5 low-level output voltage ?v dd = 4.0 to 6.0 v v ol (2) when i ol = 1 ma and the i ol for port 0.5 v each port is 1 ma or less. hysteresis voltage v his 0.1 v dd high-level threshold v th 0.4 v dd 0.8 v dd voltage low-level threshold v tl 0.25 v dd 0.6 v dd voltage electrical characteristics at ta = ?0 to +85?, v ss = 0 v, v dd = 2.5 to 6.0 v (unless otherwise specified.) schmitt characteristics continued on next page. continued from preceding page. res, int, sck, si, and osc1 with schmitt specifications * 5
no. 6278-23/39 lc651154n, 651154f, 651154l, 651152n, 651152f, 651152l parameter symbol conditions applicable pins and notes ratings unit min typ max current drain * 6 iddop (1) ?figure 2, 4 mhz v dd 26 ?200 khz to 4330 khz ma ceramic oscillator ?operating, with the output iddop (2) n-channel transistors off and the v dd 26 ports at v dd . ?output n-channel transistors off v dd 0.05 10 ? standby mode iddst v dd = 6 v ?ports at v dd , v dd = 2.5 v v dd 0.025 5 oscillator characteristics ceramic oscillator f cfosc * 7 ?figure 2, fo = 4 mhz osc1, osc2 3920 4000 4080 khz oscillator frequency * 8t cfs ?figure 3, fo = 4 mhz 10 ms pull-up resistor rpp ?output n-channel transistors off pull-up resistor 814 30 k i/o ports ?v in = v ss , v dd = 5 v specification ports res ru v in = v ss , v dd = 5 v res 200 500 800 external reset characteristics t rst see figure 4. reset time ?f = 1 mhz pin capacitances cp ?with all pins other than the pin 10 pf being tested at v in = v ss . serial clock input clock cycle time t ckcy (1) figure 5 sck 2.0 output clock cycle time t ckcy (2) figure 5 sck 64 t cyc * 9 input clock low-level pulse t ckl (1) figure 5 sck 0.6 width output clock low-level pulse t ckl (2) figure 5 sck 32 t cyc width input clock high-level pulse t ckh (1) figure 5 sck 0.6 width output clock high-level t ckh (2) figure 5 sck 32 t cyc pulse width serial input data setup time t ick ?stipulated with respect to the si 0.2 rising edge of sck. ? ?figure 5 data hold time t cki si 0.2 serial output ?stipulated with respect to the falling edge of sck. ?with an external resistor of 1 k so 0.4 output delay time t cko and an external capacitor of 50 pf on only the n-channel open-drain pins. ?figure 5 pulse output function period t pcy ?figure 6 pe0 64 t cyc ?t cyc = 4 system clock period high-level pulse width t ph ?with an external resistor of pe0 32 t cyc 1 k and an external ?0% capacitor of 50 pf on only low-level pulse width t pl the n-channel open-drain pe0 32 t cyc pins. ?0% continued from preceding page. continued on next page.
no. 6278-24/39 lc651154n, 651154f, 651154l, 651152n, 651152f, 651152l continued from preceding page. parameter symbol conditions applicable pins ratings unit and notes min typ max resolution v dd = 3 to 6 v 8 bit absolute precision av + = v dd a/d converter speed 1/1 v dd = 3.5 to 6 v 1 2 lsb av = v ss a/d converter speed 1/2 v dd = 3.5 to 6 v 1 2 when the a/d converter 24 312 speed is normal (1/1), v dd = 3.5 to 6 v (t cyc = (t cyc = namely 26 t cyc 0.92 ?) 12 ?) conversion time tcad when the a/d converter 47 612 ? speed is one half (1/2), v dd = 3 to 6 v (t cyc = (t cyc = namely 51 t cyc 0.92 ?) 12 ?) input reference voltage av + av + av v dd v av av v ss av+ input reference current irif av+ = v dd , av = v ss av + , av 200 500 800 ? range analog input voltage vain v dd = 3 to 6 v ad0 to ad7 av av + v range including the output off ad0 to ad7 leakage current. (the i/o 1 v ain = v dd shared analog port input current iain function ports ? v ain = v ss have open- ? drain specifications.) cw when pe1 has the wdr 0.01 ?% f open drain specifications. recommended rw when pe1 has the wdr 680 ?% k constants * 10 open drain specifications. ri when pe1 has the wdr 100 ?% open drain specifications. clear time (discharge) t wct figure 7 wdr 10 ? clear period (charge) t wccy figure 7 wdr 4.2 ms a/d converter characteristics watchdog timer notes:1. allowed up to the amplitude generated when the oscillator shown in figure 2 is used with the recommended circuit consta nts and driven by the ic. 2. the average over a 100 ms period. 3. the operating v dd supply voltage must be maintained from the point the halt instruction is executed until the ic has fully entered the standby state. applications must also assure that no chattering occurs on the pa3 pin during the halt instruction execution cycle. 4. recommended circuit constants that have been verified to oscillate stably according to the oscillator element manufacturer us ing the sanyo- stipulated oscillator characteristics evaluation board. 5. the osc1 pin will have schmitt characteristics when external clock oscillator is selected with the two-pin rc oscillator opti on. 6. these are the results of testing using our (sanyo?) characteristics evaluation board with the recommended circuit constants used as external components. the current flowing in the ic? output transistors and transistors that have pull-up resistors is not included. 7. f cfosc is the frequency when the recommended circuit constants from table 1 are used as external components. 8. indicates the time required to achieve stable oscillation from the point v dd rises above the lower limit of the operating voltage range (see figure 3). 9. t cyc = 4 the system clock period 10. if the application could be used in an environment in which condensation is possible, extra care with respect to the leakage between pe1 and adjacent pins and leakage associated with external resistors and capacitor is required during design.
no. 6278-25/39 lc651154n, 651154f, 651154l, 651152n, 651152f, 651152l figure 1 external clock input waveform figure 2 ceramic oscillator circuit external clock open ceramic oscillator element
no. 6278-26/39 lc651154n, 651154f, 651154l, 651152n, 651152f, 651152l figure 4 oscillation stabilization time figure 5 reset circuit note: if the power supply rise time is zero, the reset time when cres = 0.1 ? will be between 10 and 100 ms. if the power supply rise time is long, increase the value of cres so that the reset time is at least 10 ms. table 1 recommended ceramic oscillator circuit constants 4 mhz (murata mfg. co., ltd.) c1 33 pf ?0% csa4.00mg c2 33 pf ?0% cst4.00mgw (internal capacitor) r 0 4 mhz (kyocera corporation) c1 33 pf ?0% kbr4.0msa c2 33 pf ?0% kbr4.0mks (internal capacitor) r 0 stable oscillation oscillation stabilization time t cfs lower limit for the operating supply voltage
no. 6278-27/39 lc651154n, 651154f, 651154l, 651152n, 651152f, 651152l figure 5 serial i/o timing figure 6 port pe0 pulse output timing figure 7 watchdog timer waveform input data output data load circuit the load conditions are the same as those in figure 4. t wccy : the charge time due to the time constant of the circuit consisting of the external components cw, rw, and rl. t wct : the discharge time due to software processing.
no. 6278-28/39 lc651154n, 651154f, 651154l, 651152n, 651152f, 651152l lc651154l, 651152l parameter symbol conditions applicable pins and notes ratings unit maximum supply voltage v dd max v dd ?.3 to +7.0 output voltage v o osc2 allowed up to the generated voltage. input voltage v i (1) osc1 * 1 ?.3 to v dd + 0.3 v v i (2) test, res, av + , av ?.3 to v dd + 0.3 v io (1) pc0 to pc3, pd0 to pd3, pe0, 1, pf0 to pf3 open-drain specification ports ?.3 to +15 i/o voltage v io (2) pc0 to pc3, pd0 to pd3, pe0, 1, pf0 to pf3 pull-up resistor specification ports ?.3 to v dd + 0.3 v io (3) pa0 to pa3, pg0 to pg3 ?.3 v dd + 0.3 peak output current i op i/o ports ? to +20 i oa per single pin, averaged over 100 ms i/o ports ? to +20 the total current for pc0 to pc3, pc0 to pc3 i oa (1) pd0 to pd3, and pe0 to pe1 * 2 pd0 to pd3 ?5 to +100 ma average output current pe0 to pe1 the total current for pf0 to pf3, pg0 to pg3, pf0 to pf3 i oa (2) and pa0 to pa3 (see note 2.) * 2 pg0 to pg3 ?5 to +100 pa0 to pa3 pd max (1) ta = ?0 to +85? (dip package) 310 allowable power dissipation pd max (2) ta = ?0 to +85? (mfp package) 220 mw pd max (3) ta = ?0 to +85? (ssop package) 160 operating temperature topr ?0 to +85 ? storage temperature tstg ?5 to +125 absolute maximum ratings at ta = 25?, v ss = 0 v parameter symbol conditions applicable pins and notes ratings unit min typ max operating supply voltage v dd v dd 2.2 6.0 standby supply voltage v st ram and register values retained * 3 v dd 1.8 6.0 v ih (1) output n-channel transistors off ports c, d, e, and f with 0.7 v dd 13.5 open-drain specifications v ih (2) output n-channel transistors off ports c, d, e, and f with 0.7 v dd v dd pull-up resistor specifications v ih (3) output n-channel transistors off port a, g 0.7 v dd v dd the int, sck, and si high-level input voltage v ih (4) output n-channel transistors off pins with open-drain 0.8 v dd 13.5 specifications the int, sck, and si v v ih (5) output n-channel transistors off pins with pull-up resistor 0.8 v dd v dd specifications v ih (6) v dd = 1.8 to 6.0 v res 0.8 v dd v dd v ih (7) external clock specifications osc1 0.8 v dd v dd v il (1) output n-channel transistors off port v ss 0.2 v dd v il (2) output n-channel transistors off int, sck, si v ss 0.15 v dd low-level input voltage v il (3) output n-channel transistors off osc1 v ss 0.15 v dd v il (4) test v ss 0.2 v dd v il (5) res v ss 0.15 v dd allowable operating ranges at ta = ?0 to +85?, v ss = 0 v, v dd = 2.2 to 6.0 v (unless otherwise specified.) continued on next page.
no. 6278-29/39 lc651154n, 651154f, 651154l, 651152n, 651152f, 651152l parameter symbol conditions applicable pins ratings unit and notes min typ max operating frequency the clock may have a frequency up to 200 1040 (cycle time) fop (tcyc) 4.16 mhz when the divide-by-four internal (20) (3.84) khz (?) divider circuit option is used. external clock conditions figure 1. frequency text osc1 200 4160 khz pulse width texth, textl osc1 100 ns rise and fall times textr, textf osc1 100 ns recommended oscillator circuit constants two-pin rc oscillator cext figure 2 osc1, osc2 270 ?% pf rext 12 ?% k ceramic oscillator * 4 figure 3 see table 1. continued from preceding page. either the divide-by-three or divide-by- four internal divider circuit must be used if the clock frequency exceeds 1.040 mhz.
parameter symbol conditions applicable pins and notes ratings unit min typ max ?output n-channel transistors off ports c, d, e and f with i ih (1) (including the n-channel transistor the open-drain 5.0 off leakage current.) specifications ?v in = 13.5 v high-level input current ?output n-channel transistors off i ih (2) (including the n-channel transistor ports a and g with the 1.0 ? off leakage current.) open-drain specifications ?v in = v dd i ih (3) when an external clock is used, osc1 1.0 v in = v dd i il (1) ?output n-channel transistors off ports with the open-drain ?.0 ?v in = v ss specifications i il (2) ?output n-channel transistors off ports with the pull-up ?.3 ?.35 ma low-level input current ?v in = v ss resistor specifications i il (3) v in = v ss res ?5 ?0 ? i il (4) when an external clock is used, osc1 ?.0 v in = v ss high-level output voltage v oh ?i oh = ?0 ? ports with the pull-up v dd ?0.5 resistor specifications v ol (1) ?i ol = 3 ma port 1.5 low-level output voltage v ol (2) when i ol = 1 ma and the i ol for port 0.4 v each port is 1 ma or less. hysteresis voltage v his 0.1 v dd high-level threshold v th 0.4 v dd 0.8 v dd voltage low-level threshold v tl 0.2 v dd 0.6 v dd voltage current drain * 6 ?operating, with the output n-channel transistors off two-pin rc oscillator iddop (1) ?with the ports at v dd v dd 1.0 4 ?figure 2, fosc = 800 khz (typical) ceramic oscillator iddop (2) ? figure 3, 4 mhz, divide-by-four circuit used v dd 1.5 4 iddop (3) ? figure 3, 4 mhz, divide-by-four circuit used v dd 0.5 1 v dd = 2.2 v iddop (4) ?figure 3, 400 khz v dd 1.0 2.5 ma iddop (5) ?figure 3, 800 khz v dd 1.5 4 ?200 khz to 1024 khz, no divider circuit external clock iddop (6) ?600 khz to 3120 khz, divide-by- v dd 1.5 4 three circuit used ?800 khz to 4160 khz, divide-by- four circuit used output n-channel transistors off, v dd 0.05 10 standby mode iddst v dd = 6 v ? ports at v dd , v dd = 2.2 v v dd 0.020 4 res, int, sck, si, and osc1 with schmitt specifications * 5 no. 6278-30/39 lc651154n, 651154f, 651154l, 651152n, 651152f, 651152l electrical characteristics at ta = ?0 to +85?, v ss = 0 v, v dd = 2.2 to 6.0 v (unless otherwise specified.) schmitt characteristics continued on next page.
parameter symbol conditions applicable pins and notes ratings unit min typ max oscillator characteristics ?figure 3, fo = 400 khz osc1, osc2 392 400 408 ceramic oscillator ?figure 3, fo = 800 khz osc1, osc2 784 800 816 oscillator frequency f cfosc * 7 ?figure 3, fo = 1 mhz osc1, osc2 980 1000 1020 khz ?figure 3, fo = 4 mhz, with the osc1, osc2 3920 4000 4080 divide-by-four circuit used. ?figure 4, fo = 400 khz 10 oscillator stabilization time * 8 t cfs ?figure 4, fo = 800 khz, 1 mhz, or 10 ms 4 mhz, with the divide-by-four circuit used. two-pin rc oscillator f mosc ?figure 2, cext = 270 pf ?% osc1, osc2 290 400 841 khz oscillator frequency ?figure 2, rext = 5.6 k ?% pull-up resistor rpp ?output n-channel transistors off pull-up resistor 814 30 i/o ports ?v in = v ss , v dd = 5 v specification ports k res ru v in = v ss , v dd = 5 v res 200 500 800 external reset characteristics t rst see figure 5. reset time ?f = 1 mhz pin capacitances cp ?with all pins other than the pin 10 pf being tested at v in = v ss . serial clock input clock cycle time t ckcy (1) figure 6 sck 2.0 output clock cycle time t ckcy (2) figure 6 sck 64 t cyc * 9 input clock low-level pulse t ckl (1) figure 6 sck 2.0 width output clock low-level pulse t ckl (2) figure 6 sck 32 t cyc width input clock high-level pulse t ckh (1) figure 6 sck 2.0 width output clock high-level t ckh (2) figure 6 sck 32 t cyc pulse width serial input data setup time t ick si 0.5 ? data hold time t cki si 0.5 serial output ?stipulated with respect to the falling edge of sck. ?with an external resistor of 1 k so 1.0 output delay time t cko and an external capacitor of 50 pf on only the n-channel open-drain pins. ?figure 6 pulse output function period t pcy pe0 64 t cyc high-level pulse width t ph pe0 32 t cyc ?0% low-level pulse width tpl pe0 32 t cyc ?0% ?stipulated with respect to the rising edge of sck. ?figure 6 no. 6278-31/39 lc651154n, 651154f, 651154l, 651152n, 651152f, 651152l continued from preceding page. continued on next page. ?figure 7 ?tcyc = 4 system clock period ?with an external resistor of 1 k and an external capacitor of 50 pf on only the n-channel open-drain pins.
no. 6278-32/39 lc651154n, 651154f, 651154l, 651152n, 651152f, 651152l continued from preceding page. parameter symbol conditions applicable pins ratings unit and notes min typ max resolution 8 bit absolute precision av + = v dd ? ? lsb av = v ss when the a/d converter 99 312 ? speed is normal (1/1), (t cyc = (t cyc = namely 26 t cyc 3.84 ?) 12 ?) conversion time tcad when the a/d converter 195 612 speed is one half (1/2), (t cyc = (t cyc = namely 51 t cyc 3.84 ?) 12 ?) input reference voltage av + av + av v dd v av av v ss av + input reference current i rif av + = v dd av + , av 200 500 800 ? range av = v ss analog input voltage v ain ad0 to ad7 av av + v range including the output off ad0 to ad7 leakage current. (the i/o 1 v ain = v dd shared analog port input current i ain function ports ? v ain = v ss have open- ? drain specifications.) cw when pe1 has the wdr 0.1 ?% f open-drain specifications. recommended rw when pe1 has the wdr 680 ?% k constants * 10 open-drain specifications. ri when pe1 has the wdr 100 ?% open-drain specifications. clear time (discharge) t wct figure 8 wdr 100 ? clear period (charge) t wccy figure 8 wdr 31 ms cw when pe1 has the wdr 0.047 ?% f open-drain specifications. recommended rw when pe1 has the wdr 680 ?% k constants * 10 open-drain specifications. ri when pe1 has the wdr 100 ?% open-drain specifications. clear time (discharge) t wct figure 8 wdr 40 ? clear period (charge) t wccy figure 8 wdr 14 ms a/d converter characteristics watchdog timer notes:1. allowed up to the amplitude generated when the oscillator shown in figure 3 is used with the recommended circuit consta nts and driven by the ic. 2. the average over a 100 ms period. 3. the operating v dd supply voltage must be maintained from the point the halt instruction is executed until the ic has fully entered the standby state. applications must also assure that no chattering occurs on the pa3 pin during the halt instruction execution cycle. 4. recommended circuit constants that have been verified to oscillate stably according to the oscillator element manufacturer us ing the sanyo- stipulated oscillator characteristics evaluation board. 5. the osc1 pin will have schmitt characteristics when external clock oscillator is selected with the two-pin rc oscillator opti on. 6. these are the results of testing using our (sanyo?) characteristics evaluation board with the recommended circuit constants used as external components. the current flowing in the ic? output transistors and transistors that have pull-up resistors is not included. 7. f cfosc is the frequency when the recommended circuit constants from table 1 are used as external components. 8. indicates the time required to achieve stable oscillation from the point v dd rises above the lower limit of the operating voltage range (see figure 4). 9. t cyc = 4 the system clock period 10. if the application could be used in an environment in which condensation is possible, extra care with respect to the leakage between pe1 and adjacent pins and leakage associated with external resistors and capacitor is required during design. v dd = 3 to 6 v v dd = 2.2 to 6 v v dd = 2.2 to 6 v
no. 6278-33/39 lc651154n, 651154f, 651154l, 651152n, 651152f, 651152l figure 1 external clock input waveform figure 2 two-pin rc oscillator circuit figure 3 ceramic oscillator circuit external clock open ceramic oscillator element 0.15 v dd
no. 6278-34/39 lc651154n, 651154f, 651154l, 651152n, 651152f, 651152l figure 4 oscillation stabilization time figure 5 reset circuit note: if the power supply rise time is zero, the reset time when cres = 0.1 ? will be between 10 and 100 ms. if the power supply rise time is long, increase the value of cres so that the reset time is at least 10 ms. table 1 recommended ceramic oscillator circuit constants 4 mhz (murata mfg. co., ltd.) c1 33 pf ?0% csa4.00mg c2 33 pf ?0% cst4.00mgw (internal capacitor) r 0 4 mhz (kyocera corporation) c1 33 pf ?0% kbr4.0msa c2 33 pf ?0% kbr4.0mks (internal capacitor) r 0 1 mhz (murata mfg. co., ltd.) c1 100 pf ?0% csb1000j c2 100 pf ?0% r 3.3 k 800 khz (murata mfg. co., ltd.) c1 100 pf ?0% csb800j c2 100 pf ?0% r 3.3 k 400 khz (murata mfg. co., ltd.) c1 220 pf ?0% csb400p c2 220 pf ?0% r 3.3 k stable oscillation oscillation stabilization time t cfs lower limit for the operating supply voltage
no. 6278-35/39 lc651154n, 651154f, 651154l, 651152n, 651152f, 651152l figure 6 serial i/o timing figure 7 port pe0 pulse output timing figure 8 watchdog timer waveform input data the load conditions are the same as those in figure 5. t wccy : the charge time due to the time constant of the circuit consisting of the external components cw, rw, and rl. t wct : the discharge time due to software processing. output data load circuit
no. 6278-36/39 lc651154n, 651154f, 651154l, 651152n, 651152f, 651152l rc oscillator characteristics for the lc651154l and LC651152L figure 9 shows the rc oscillator characteristics for the lc651154l and LC651152L. however, the sample-to-sample variation in the lc651154l and LC651152L rc oscillator frequency described below does occur. 1) when: v dd = 2.2 to 6.0 v, ta = ?0 to +85? external constants: cext = 270 pf rext = 12.0 k f mosc will be: 290 khz f mosc 841 khz therefore, only the above circuit constants are recommended. if use of circuit constants other than the above is unavoidable, they must be in the following ranges. cext = 150 to 390 pf rext = 3 to 20 k (see figure 9.) note 8. the oscillator frequency must be in the range 350 to 850 khz when v dd = 5.0 v and ta = 25?. note 9. applications must be designed to have adequate margins so that the oscillator frequency falls in the operating clock frequency range (see the oscillator divider option table) for the voltage range v dd = 2.2 to 6.0 v and for the temperature range ta = ?0 to 85?. figure 9 rc oscillator frequency data (representative values) these characteristics curves are for reference purposes only and are not guaranteed.
notes on printed circuit board design this section describes points that require care concerning noise from the point of view of the microcontroller and presents means of preventing associated problems when designing a printed circuit board to use with these products in a mass produced end product. the ideas presented in this section are effective design techniques for preventing and avoiding problems (such as incorrect microcontroller operation and program failures) due to noise. 1. the v dd and v ss power supply pins insert capacitors that meet the following conditions between the v dd and v ss power supply pins. the lengths of the lines between the v dd and v ss pins and the capacitors c1 and c2 should be as close to exactly equal as possible (l1 = l1? l2 = l2?. furthermore, these distances should be as short as possible. insert two capacitors, c1 and c2 in parallel, with c1 having a large capacitance and c2 having a small capacitance. the v dd and v ss lines in the printed circuit board pattern should be wider than any other lines in the pattern. 2. the osc1 and osc2 clock i/o pins ?if the ceramic oscillator option is selected (see figure 2-1.) keep the lines between the clock i/o pins (input: osc1, output: osc2) and the external components as short as possible (the distance losc in the figure). make the length of the lines (lvss + l1 and lvss + l2) from the microcontroller v ss pin to the v ss side of the capacitors connected to the oscillator element as short as possible. ? ss line for the oscillator circuit and other v ss line should branch from a point nearest to the v ss pin. due to the capacitances of the wiring on the printed circuit board, it may be necessary to modify the values of the oscillator circuit constants (including the values of the capacitors c1 and c2 and the limiting resistor rd) from the values presented in this catalog. we recommend consulting the manufacturer of the oscillator element with regard to these circuit constants. ?if the 2-pin rc oscillator option is selected (figure 2-2) keep the lines between the clock i/o pins (input: osc1, output: osc2) and the external components (the capacitor cext and the resistor rext) as short as possible (the distance losc in the figure). make the length of the lines (lvss + lc) from the microcontroller v ss pin to the v ss side of the capacitor functioning as the oscillator element as short as possible. take the v ss used by the oscillator circuit (as well as other v ss usages) from a point as close as possible to the v ss pin. ?if the external oscillator option is selected (figure 2-3) keep the line between the clock input pin (osc1) and the external oscillator circuit as short as possible (the distance losc in the figure). leave the clock output pin (osc2) open. make the length (losc) of the lines to the v dd and v ss pins used by the external oscillator as short as possible. ?other points that apply to all oscillator circuits: keep all lines that carry signals that change rapidly, signals that have large amplitudes due to being connected to the medium- voltage handling capacity ports, or signals that carry large currents as far away from the oscillator circuit as possible. also, do not allow such signal lines to cross any clock-signal related lines. no. 6278-37/39 lc651154n, 651154f, 651154l, 651152n, 651152f, 651152l figure 2-2 sample oscillator circuit 2 (2-pin rc oscillator) figure 2-1 sample oscillator circuit 1 (ceramic oscillator) figure 2-3 sample oscillator circuit 3 (external oscillator) external oscillator
3. res: reset pin keep the length of lines (lres in the figure) from the res pin to external circuits as short as possible. keep the length of the lines (l1 and l2) to the capacitor (cres) inserted between res and v ss as short as possible. 4. test: test pin keep the length of the line (l) from the test pin to the v ss pin as short as possible. run the line from the test pin to the v ss pin as close to the v ss pin as possible. 5. ad0 to ad7: analog input pins analog input pin lines, such as those used to connect to an a/d converter input pin or a comparator input pin should be connected so as to meet the following conditions. keep the line (l1) between the limiting resistor (rl) and the analog input pin as short as possible. locate the capacitor inserted between the analog input pins and the av- pin (the a/d converter reference voltage input pin) as close as possible to the av- input pin. that is, make the line length l1 + l2 as short as possible. 6. i/o pins all of the pins on these products function as both input and output pins. when used as an input pin, insert a limiting resistor, and keep the length of the line to that pin as short as possible. supplement: this is not only useful in printed circuit board design, but is also useful in preventing and avoiding problems (such as incorrect microcontroller operation and program failures) by taking the program specifications and microcontroller option selections described below into consideration. if signals are input from external sources when the microcontroller power supply is unstable, select the medium- voltage handling capacity (n-channel open drain) output as the output type option for that input pin, and also insert a limiting resistor in the input circuit. always implement key chattering exclusion measures for external signals applied to microcontroller input pins. the pin output data should be re-output periodically with an output instruction (op or spb). no. 6278-38/39 lc651154n, 651154f, 651154l, 651152n, 651152f, 651152l figure 3 res pin wiring figure 4 test pin wiring figure 5 analog input pin wiring external circuit external circuit (sensor block) analog input pin
ps no. 6278-39/39 lc651154n, 651154f, 651154l, 651152n, 651152f, 651152l when reading data input to a pin that can function as either input or output, set the output value for that pin to 1 every time the input is read using an output instruction (op or spb). 7. unused pins see the users manual for the product or refer to the pin functions as described in the semiconductor report for the device. this catalog provides information as of september, 1999. specifications and information herein are subject to change without notice. specifications of any and all sanyo products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer? products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer? products or equipment. sanyo electric co., ltd. strives to supply high-quality high-reliability products. however, any and all semiconductor products fail with some probability. it is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. in the event that any or all sanyo products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of sanyo electric co., ltd. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equipment, refer to the ?elivery specification for the sanyo product that you intend to use. information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. sanyo believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.

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